The present invention relates to an encoding device encoding an image signal.
FIG. 12 shows a conventional encoding device shown in “All about MPEG-4 (MPEG-4 no subete)” (Kogyo Chosakai), pages 39-40.
In FIG. 12, reference numeral 1 denotes an image signal input circuit receiving an image signal (e.g., R, G and B signals) from an image signal generating device such as a camera, not shown, and converting the image signal into Y, Cb and Cr signals, and dividing the signals into macroblocks to generate block-divided image signals. Reference numeral 2 denotes an image encoding circuit receiving and encoding the block-divided image signals output from the image signal input circuit 1. Reference numeral 3 denotes a transmission path for transmitting the encoded image signals.
The image encoding circuit 2 has a subtractor 2a receiving the input signal as a first input. The output of the subtractor 2a is passed through a DCT circuit 2b, and a quantizer 2c, and input to a DC/AC predictor 2d and an inverse quantizer 2f. The output of the DC/AC predictor 2d is supplied to a first input terminal of a variable length coding circuit 2e, which outputs a bit stream. The output of the inverse quantizer 2f is passed through an inverse DCT circuit 2g and supplied to a first input terminal of an adder 2h. The output of the adder 2h is supplied to a memory 2j, whose output is supplied to a first input terminal of a predicted image generating circuit 2k and a first input terminal of a motion detection circuit 2m. Supplied to a second input terminal of the motion detection circuit 2m is the input signal to the image encoding circuit 2 (the output of the image signal input circuit 1). The output of the motion detection circuit 2m is supplied to a second input terminal of the predicted image generating circuit 2k and the motion vector predictor 2i. The output of the motion vector predictor 2i is supplied to a second input terminal of the variable length coding circuit CIRCUIT 2e. The output of the predicted image generating circuit 2k is supplied to a second input terminal of the subtractor 2a and a second input terminal of the adder 2h. 
The output of the image encoding circuit 2 is passed through the transmission path 3 and supplied as a bit stream to a decoding device, not shown.
The operation is next described. The block-divided image signals output from the image signal input circuit 1 and input to the image encoding circuit 2 are signals having been divided into macroblocks, which are basic units of processing, as shown in FIG. 13. That is, when the input image signal is of 4:2:0, 16 pixels by 16 lines of the luminance signal (Y) has the same size on the screen as the 8 pixels by 8 lines of chrominance signals (Cb, Cr), so that 6 blocks of 8 pixels by 8 lines form one macroblock. Here, it is assumed that the input video object plane (VOP) is rectangular, and is identical to a frame.
The image encoding circuit 2 applies discrete cosine transform (DCT) to each block, and then performs quantization. The quantized DCT coefficients are supplied to the DC/AC predictor 2d, where coefficient prediction is performed, and then subjected to variable length coding together with the additional information such as the quantization parameters. This is intra-coding. The VOP for which the intra-coding is performed on all the macroblocks is called an I-VOP.
The quantized DCT coefficients are subjected to inverse quantization and inverse DCT to be decoded, and the decoded image is stored in the memory 2j. The decoded image in the memory 2j is utilized when inter-coding is performed.
In the case of inter-coding, the motion detection circuit 2m detects the motion vector indicating the motion of the input macroblock. The motion vector indicates the position of the decoded image among the decoded images stored in the memory 2j at which the difference with respect to the input macroblock is minimum. The predicted image generating circuit 2k generates a predicted image based on the motion vector. Then a difference between the input macroblock and the predicted image is determined, and the difference signal is subjected to DCT and quantization. The quantized conversion coefficients are variable-length encoded together with the predictive-coded motion vector, supplied via the motion vector predictor 2i, and the additional information such as the quantization parameters. The quantized DCT coefficients are subjected to inverse quantization and inverse DCT, and added (at the adder 2h) to the predicted image, and stored in the memory 2j. 
The bit rate on the transmission path 3 is monitored, and when the transmission speed is lowered due for example to the conditions of the line, in a stream distribution in internet, the frame rate at which the encoding is performed at the image encoding circuit 2 is lowered, so that the encoding is in conformity with the transmission speed. In this case, the images are displayed at the decoding device, not shown, with the frame rate of the decoded images being varied depending on the transmission speed.
In the convention encoding device described above, the image encoding circuit 2 needs to lower the frame rate of the images transmitted to the decoding device when the transmission speed is lowered. In this case, the images decoded at the decoding device may be displayed with frames skipped, because the data of the frames of the images is partially missing.